1. Field of the Invention
The present invention relates to a switch set of bi-directional shift register modules, and more particularly, to a switch set of bi-directional shift register modules controlled by clock signals.
2. Description of the Prior Art
FIG. 1 is a diagram illustrating a conventional bi-directional shift register circuit 100. The bi-directional shift register circuit 100 comprises shift register module 110 and switch set 120. The shift register module 110 comprises shift registers SR1, SR2, and SR3. The switch set 120 comprises switch devices SW1, SW2, and SW3. Each of the shift registers SR1˜SR3 is a one-to-one shift register. That is, each shift register only receives signal outputted from either the previous shift register or the next shift register as input signal. For example, the shift register SR2 receives either the shift register signal SRO1 from the shift register SR1 or the shift register signal SRO3 from the shift register SR3. Each of the shift registers SR1˜SR3 comprises a first input end I5, a second input end I6, and a third input end I7. The first input end I5 receives a shift register signal, the second input end I6 (clock input end) receives a clock signal, and the third input end I7 (clock input end) receives an inversed clock signal of the clock signal. Each of the shift registers SR1˜SR3 samples the received shift register signal and output shift register signal according to the clock signal and the inversed clock signal. The shift register module 110 controls the direction of the transmission of the shift register signals of the shift registers SR1˜SR3 by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 110 set to transmit shift register signals in a first direction (the forward direction), each second input end I6 of the shift registers SR1˜SR3 is input with the clock signal CLK, and each third input end I7 of the shift registers SR1˜SR3 is input with the clock signal XCLK. In this way, the shift register module 110 transmits shift register signals in the first direction. When the shift register module 110 is set to transmit shift register signals in the reverse direction of the forward direction, each second input end I6 of the shift registers SR1˜SR3 is input with the clock signal XCLK, and each third input end I7 of the shift registers SR1˜SR3 is input with the clock signal CLK. In this way, the shift register module 110 transmits shift register signals in the reverse of the first direction.
As shown in FIG. 1, the switch device SW1 controls the input signal SRI1 of the shift register SR1. The switch device SW1 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM11 and CM12. The control end C1 of the switch device SW1 receives the control signal VBD, the control end C2 of the switch device SW1 receives the control signal XBD, and the control end C3 of the switch device SW1 receives the control signal VBD. The input end I1 of the switch device SW1 receives a start signal ST, the input end I2 of the switch device SW1 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2. The output ends O1 and O2 of the switch device SW1 are both coupled to the input end I5 of the shift register SR1 for transmitting the input signal SRI1 to the shift register SR1. The switch units CM11 and CM12 can be realized with any components having switch functions, for example, Complementary Metal Oxide Semiconductor (CMOS). The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with N-type Metal Oxide Semiconductor (NMOS) and the other one of the switch units of the CMOS is realized with P-type Metal Oxide Semiconductor (PMOS). As shown in FIG. 1, the first end of the PMOS of the switch unit CM11 is coupled to the input end I1, the second end of the PMOS of the switch unit CM11 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM11 is coupled to the control end C1. The first end of the NMOS of the switch unit CM11 is coupled to the input end I1, the second end of the NMOS of the switch unit CM11 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM11 is coupled to the control end C2. The first end of the PMOS of the switch unit CM12 is coupled to the input end I2, the second end of the PMOS of the switch unit CM12 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM12 is coupled to the control end C2. The first end of the NMOS of the switch unit CM12 is coupled to the input end I2, the second end of the NMOS of the switch unit CM12 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM12 is coupled to the control end C3.
The switch device SW2 controls the input signal SRI2 of the shift register SR2. The switch device SW2 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM21 and CM22. The control end C1 of the switch device SW2 receives the control signal VBD, the control end C2 of the switch device SW2 receives the control signal XBD, and the control end C3 of the switch device SW2 receives the control signal VBD. The input end I1 of the switch device SW2 is coupled to the output end O3 of the shift register SR1 for receiving the shift register signal SRO1, the input end I2 of the switch device SW2 is coupled to the output end O3 of the shift register SR3 for receiving the shift register signal SRO3. The output ends O1 and O2 of the switch device SW2 are both coupled to the input end I5 of the shift register SR2 for transmitting the input signal SRI2 to the shift register SR2. The switch units CM21 and CM22 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS transistor is realized with PMOS. As shown in FIG. 1, the first end of the PMOS of the switch unit CM21 is coupled to the input end I1, the second end of the PMOS of the switch unit CM21 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM21 is coupled to the control end C1. The first end of the NMOS of the switch unit CM21 is coupled to the input end I1, the second end of the NMOS of the switch unit CM21 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM21 is coupled to the control end C2. The first end of the PMOS of the switch unit CM22 is coupled to the input end I2, the second end of the PMOS of the switch unit CM22 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM22 is coupled to the control end C2. The first end of the NMOS of the switch unit CM22 is coupled to the input end I2, the second end of the NMOS of the switch unit CM22 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM22 is coupled to the control end C3.
The switch device SW3 controls the input signal SRI3 of the shift register SR3. The switch device SW3 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM31 and CM32. The control end C1 of the switch device SW3 receives the control signal VBD, the control end C2 of the switch device SW3 receives the control signal XBD, and the control end C3 of the switch device SW3 receives the control signal VBD. The input end I1 of the switch device SW3 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2, the input end I2 of the switch device SW3 receives the start signal ST. The output ends O1 and O2 of the switch device SW3 are both coupled to the input end I5 of the shift register SR3 for transmitting the input signal SRI3 to the shift register SR3. The switch units CM31 and CM32 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS transistor is realized with PMOS. As shown in FIG. 1, the first end of the PMOS of the switch unit CM31 is coupled to the input end I1, the second end of the PMOS of the switch unit CM31 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM31 is coupled to the control end C1. The first end of the NMOS of the switch unit CM31 is coupled to the input end I1, the second end of the NMOS of the switch unit CM31 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM31 is coupled to the control end C2. The first end of the PMOS of the switch unit CM32 is coupled to the input end I2, the second end of the PMOS of the switch unit CM32 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM32 is coupled to the control end C2. The first end of the NMOS of the switch unit CM32 is coupled to the input end I2, the second end of the NMOS of the switch unit CM32 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM32 is coupled to the control end C3.
When the shift register circuit 100 is set to operate in the forward direction, the control signal VBD of the switch set 120 is set at a first predetermined voltage (for example, high voltage), and the control signal XBD of the switch set 120 is set a second predetermined voltage (for example, low voltage). In this way, the switch unit CM11 of the switch device SW1 is turned on, the switch unit CM12 of the switch device SW1 is turned off, and consequently the start signal ST is transmitted to the input end I5 of the shift register SR1 as the input signal SRI1. The switch unit CM21 of the switch device SW2 is turned on, the switch unit CM22 of the switch device SW2 is turned off, and consequently the shift register signal SRO1 is transmitted to the input end I5 of the shift register SR2 as the input signal SRI2. The switch unit CM31 of the switch device SW3 is turned on, the switch unit CM32 of the switch device SW3 is turned off, and consequently the shift register signal SRO2 is transmitted to the input end I5 of the shift register SR3 as the input signal SRI3.
On the other hand, when the shift register circuit 100 is set to operate in the reverse direction, the control signal VBD of the switch set 120 is set at the second predetermined voltage, and the control signal XBD of the switch set 120 is set at the first predetermined voltage. In this way, the switch unit CM12 of the switch device SW1 is turned on, the switch unit CM11 of the switch device SW1 is turned off, and consequently the shift register signal SRO2 is transmitted to the input end I5 of the shift register SR1 as the input signal SRI1. The switch unit CM22 of the switch device SW2 is turned on, the switch unit CM21 of the switch device SW2 is turned off, and consequently the shift register signal SRO3 is transmitted to the input end I5 of the shift register SR2 as the input signal SRI2. The switch unit CM32 of the switch device SW3 is turned on, the switch unit CM31 of the switch device SW3 is turned off, and consequently the start signal ST is transmitted to the input end I5 of the shift register SR3 as the input signal SRI3.
The drawback of the conventional switch set 120 is that the control signals VBD and XBD have to respectively keep at the first predetermined voltage and the second predetermined voltage when the shift register circuit 100 is set to operate in the forward direction, and the control signals VBD and XBD have to respectively keep at the second predetermined voltage and the first predetermined voltage when the shift register circuit 100 is set to operate in the reverse direction. Due to the control signals VBD and XBD have to keep at a fixed predetermined voltage for long time, consequently, the stay of the control signals VBD and XBD causes aging of the switch components, which reduce the lifetime of the switch components, especially when the switch components are amorphous silicon (a-Si) thin film transistor (TFT).
FIG. 2 is a diagram illustrating another conventional bi-directional shift register circuit 200. The bi-directional shift register circuit 200 comprises shift register module 210 and switch set 220. The shift register module 210 comprises shift registers SR1, SR2, and SR3. The switch set 220 comprises switch devices SW11, SW12, SW21, SW22, SW31, and SW32. Each of the shift registers SR1˜SR3 is a two-to-one shift register. That is, each shift register receives signals outputted both from the previous shift register and the next shift register as input signals. For example, the shift register SR2 receives both of the shift register signal SRO1 from the shift register SR1 and the shift register signal SRO3 from the shift register SR3. Each of the shift registers SR1˜SR3 comprises a first input end I5, a second input end I6, a third input end I7, and a fourth input end I8. The first input end I5 receives a shift register signal, the second input end I6 (clock input end) receives a clock signal, the third input end I7 (clock input end) receives the inversed clock signal of the clock signal, and the fourth input end I8 receives another shift register signal. Each of the shift registers SR1˜SR3 samples the received shift register signals and is triggered to output shift register signals according to the clock signal and the inversed clock signal of the clock signal. The shift register module 210 controls the direction of the transmission of the shift register signals of the shift registers SR1˜SR3 by adjusting clock signal CLK and XCLK. The clock signal XCLK is the inversed clock signal of the clock signal CLK. For example, when the shift register module 110 is set to transmit shift register signals in the forward direction, each second input end I6 of the shift registers SR1˜SR3 is input with the clock signal CLK, and each third input end I7 of the shift registers SR1˜SR3 is input with the clock signal XCLK. In this way, the shift register module 210 transmits shift register signals in the forward direction. When the shift register module 210 is set to transmit shift register signals in the reverse direction, each second input end I6 of the shift registers SR1˜SR3 is input with the clock signal XCLK, and each third input end I7 of the shift registers SR1˜SR3 is input with the clock signal CLK. In this way, the shift register module 210 transmits shift register signals in the reverse direction.
As shown in FIG. 2, the switch device SW11 controls the input signal SRI11 of the shift register SR1. The switch device SW12 controls the input signal SRI12 of the shift register SR1. The switch device SW11 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM11 and CM12. The control end C1 of the switch device SW11 receives the control signal VBD, the control end C2 of the switch device SW11 receives the control signal XBD, and the control end C3 of the switch device SW11 receives the control signal VBD. The input end I1 of the switch device SW11 receives the start signal ST, the input end I2 of the switch device SW11 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2. The output ends O1 and O2 of the switch device SW11 are both coupled to the first input end I5 of the shift register SR1 for transmitting signals to the shift register SR1 as the input signals SRI11. The switch units CM11 and CM12 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM11 is coupled to the input end I1, the second end of the PMOS of the switch unit CM11 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM11 is coupled to the control end C1. The first end of the NMOS of the switch unit CM11 is coupled to the input end I1, the second end of the NMOS of the switch unit CM11 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM11 is coupled to the control end C2. The first end of the PMOS of the switch unit CM12 is coupled to the input end I2, the second end of the PMOS of the switch unit CM12 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM12 is coupled to the control end C2. The first end of the NMOS of the switch unit CM12 is coupled to the input end I2, the second end of the NMOS of the switch unit CM12 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM12 is coupled to the control end C3.
The switch device SW12 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM13 and CM14. The control end C1 of the switch SW12 receives the control signal XBD, the control end C2 of the switch SW12 receives the control signal VBD, and the control end C3 of the switch SW12 receives the control signal XBD. The input end I1 of the switch device SW12 receives the start signal ST, the input end I2 of the switch device SW12 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2. The output ends O1 and O2 of the switch device SW12 are both coupled to the second input end I8 of the shift register SR1 for transmitting signals to the shift register SR2 as the input signal SRI12. The switch units CM13 and CM14 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM13 is coupled to the input end I1, the second end of the PMOS of the switch unit CM13 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM13 is coupled to the control end C1. The first end of the NMOS of the switch unit CM13 is coupled to the input end I1, the second end of the NMOS of the switch unit CM13 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM13 is coupled to the control end C2. The first end of the PMOS of the switch unit CM14 is coupled to the input end I2, the second end of the PMOS of the switch unit CM14 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM14 is coupled to the control end C2. The first end of the NMOS of the switch unit CM14 is coupled to the input end I2, the second end of the NMOS of the switch unit CM14 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM14 is coupled to the control end C3.
The switch device SW21 controls the input signal SRI21 of the shift register SR2. The switch device SW22 controls the input signal SRI22 of the shift register SR2. The switch device SW21 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM21 and CM22. The control end C1 of the switch device SW21 receives the control signal VBD, the control end C2 of the switch device SW21 receives the control signal XBD, and the control end C3 of the switch device SW21 receives the control signal VBD. The input end I1 of the switch device SW21 is coupled to the output end O3 of the shift register SR1 for receiving the shift register signal SRO1, the input end I2 of the switch device SW21 is coupled to the output end O3 of the shift register SR3 for receiving the shift register signal SRO3. The output ends O1 and O2 of the switch device SW21 are both coupled to the first input end I5 of the shift register SR2 for transmitting signals to the shift register SR2 as the input signals SRI21. The switch units CM21 and CM22 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM21 is coupled to the input end I1, the second end of the PMOS of the switch unit CM21 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM21 is coupled to the control end C1. The first end of the NMOS of the switch unit CM21 is coupled to the input end I1, the second end of the NMOS of the switch unit CM21 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM21 is coupled to the control end C2. The first end of the PMOS of the switch unit CM22 is coupled to the input end I2, the second end of the PMOS of the switch unit CM22 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM22 is coupled to the control end C2. The first end of the NMOS of the switch unit CM22 is coupled to the input end I2, the second end of the NMOS of the switch unit CM22 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM22 is coupled to the control end C3.
The switch device SW22 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM23 and CM24. The control end C1 of the switch SW22 receives the control signal XBD, the control end C2 of the switch SW22 receives the control signal VBD, and the control end C3 of the switch SW22 receives the control signal XBD. The input end I1 of the switch device SW22 is coupled to the output end O3 of the shift register SR1 for receiving the shift register signal SRO1, the input end I2 of the switch device SW22 is coupled to the output end O3 of the shift register SR3 for receiving the shift register signal SRO3. The output ends O1 and O2 of the switch device SW22 are both coupled to the second input end I8 of the shift register SR2 for transmitting signals to the shift register SR2 as the input signal SRI12. The switch units CM23 and CM24 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM23 is coupled to the input end I1, the second end of the PMOS of the switch unit CM23 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM23 is coupled to the control end C1. The first end of the NMOS of the switch unit CM23 is coupled to the input end I1, the second end of the NMOS of the switch unit CM23 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM23 is coupled to the control end C2. The first end of the PMOS of the switch unit CM24 is coupled to the input end I2, the second end of the PMOS of the switch unit CM24 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM24 is coupled to the control end C2. The first end of the NMOS of the switch unit CM24 is coupled to the input end I2, the second end of the NMOS of the switch unit CM24 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM24 is coupled to the control end C3.
The switch device SW31 controls the input signal SRI31 of the shift register SR3. The switch device SW32 controls the input signal SRI32 of the shift register SR3. The switch device SW31 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM31 and CM32. The control end C1 of the switch device SW31 receives the control signal VBD, the control end C2 of the switch device SW31 receives the control signal XBD, and the control end C3 of the switch device SW31 receives the control signal VBD. The input end I1 of the switch device SW31 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2, the input end I2 of the switch device SW31 receives the start signal ST. The output ends O1 and O2 of the switch device SW31 are both coupled to the first input end I5 of the shift register SR3 for transmitting signals to the shift register SR3 as the input signals SRI31. The switch units CM31 and CM32 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switch units. One of the switch units of the CMOS transistor is realized with NMOS and the other one of the switch units of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM31 is coupled to the input end I1, the second end of the PMOS of the switch unit CM31 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM31 is coupled to the control end C1. The first end of the NMOS of the switch unit CM31 is coupled to the input end I1, the second end of the NMOS of the switch unit CM31 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM31 is coupled to the control end C2. The first end of the PMOS of the switch unit CM32 is coupled to the input end I2, the second end of the PMOS of the switch unit CM32 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM32 is coupled to the control end C2. The first end of the NMOS of the switch unit CM32 is coupled to the input end I2, the second end of the NMOS of the switch unit CM32 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM32 is coupled to the control end C3.
The switch device SW32 comprises three control ends C1, C2, and C3, two input ends I1, and I2, two output ends O1, and O2, and two switch units CM33 and CM34. The control end C1 of the switch device SW32 receives the control signal XBD, the control end C2 of the switch SW32 receives the control signal VBD, and the control end C3 of the switch SW32 receives the control signal XBD. The input end I1 of the switch device SW32 is coupled to the output end O3 of the shift register SR2 for receiving the shift register signal SRO2, the input end I2 of the switch device SW32 receives the start signal ST. The output ends O1 and O2 of the switch device SW32 are both coupled to the second input end I8 of the shift register SR3 for transmitting signals to the shift register SR3 as the input signal SRI32. The switch units CM33 and CM34 can be realized with any components having switch functions, for example, CMOS. The CMOS transistor comprises two switches. One of the switches of the CMOS transistor is realized with NMOS and the other one of the switches of the CMOS is realized with PMOS. As shown in FIG. 2, the first end of the PMOS of the switch unit CM33 is coupled to the input end I1, the second end of the PMOS of the switch unit CM33 is coupled to the output end O1, and the control end of the PMOS of the switch unit CM33 is coupled to the control end C1. The first end of the NMOS of the switch unit CM33 is coupled to the input end I1, the second end of the NMOS of the switch unit CM33 is coupled to the output end O1, and the control end of the NMOS of the switch unit CM33 is coupled to the control end C2. The first end of the PMOS of the switch unit CM34 is coupled to the input end I2, the second end of the PMOS of the switch unit CM34 is coupled to the output end O2, and the control end of the PMOS of the switch unit CM34 is coupled to the control end C2. The first end of the NMOS of the switch unit CM34 is coupled to the input end I2, the second end of the NMOS of the switch unit CM34 is coupled to the output end O2, and the control end of the NMOS of the switch unit CM34 is coupled to the control end C3.
When the shift register circuit 200 is set to operate in the forward direction, the control signal VBD of the switch set 220 is set at a first predetermined voltage (for example, high voltage), and the control signal XBD of the switch set 220 is set a second predetermined voltage (for example, low voltage). In this way, the switch unit CM11 of the switch device SW11 is turned on, the switch unit CM12 of the switch device SW11 is turned off, and consequently the start signal ST is transmitted to the first input end I5 of the shift register SR1 as the input signal SRI11; the switch unit CM14 of the switch device SW12 is turned on, the switch unit CM13 of the switch device SW12 is turned off, and consequently the shift register signal SRO2 is transmitted to the second input end I8 of the shift register SR1 as the input signal SRI12. The switch unit CM21 of the switch device SW21 is turned on, the switch unit CM22 of the switch device SW21 is turned off, and consequently the shift register signal SRO1 is transmitted to the first input end I5 of the shift register SR2 as the input signal SRI21; the switch unit CM24 of the switch device SW22 is turned on, the switch unit CM23 of the switch device SW22 is turned off, and consequently the shift register signal SRO3 is transmitted to the second input end I8 of the shift register SR2 as the input signal SRI22. The switch unit CM31 of the switch device SW31 is turned on, the switch unit CM32 of the switch device SW31 is turned off, and consequently the shift register signal SRO2 is transmitted to the first input end I5 of the shift register SR3 as the input signal SRI31; the switch unit CM34 of the switch device SW32 is turned on, the switch unit CM33 of the switch device SW32 is turned off, and consequently the start signal ST is transmitted to the second input end I8 of the shift register SR3 as the input signal SRI32.
On the other hand, when the shift register circuit 200 is set to operate in the reverse direction, the control signal VBD of the switch set 220 is set at the second predetermined voltage, and the control signal XBD of the switch set 220 is set at the first predetermined voltage. In this way, the switch unit CM12 of the switch device SW11 is turned on, the switch unit CM11 of the switch device SW11 is turned off, and consequently the shift register signal SRO2 is transmitted to the first input end I5 of the shift register SR1 as the input signal SRI11; the switch unit CM13 of the switch device SW12 is turned on, the switch unit CM14 of the switch device SW12 is turned off, and consequently the start signal ST is transmitted to the second input end I8 of the shift register SR1 as the input signal SRI12. The switch unit CM22 of the switch device SW21 is turned on, the switch unit CM21 of the switch device SW21 is turned off, and consequently the shift register signal SRO3 is transmitted to the first input end I5 of the shift register SR2 as the input signal SRI21; the switch unit CM23 of the switch device SW22 is turned on, the switch unit CM24 of the switch device SW22 is turned off, and consequently the shift register signal SRO1 is transmitted to the second input end I8 of the shift register SR2 as the input signal SRI22. The switch unit CM32 of the switch device SW31 is turned on, the switch unit CM31 of the switch device SW31 is turned off, and consequently the start signal ST is transmitted to the first input end I5 of the shift register SR3 as the input signal SRI31; the switch unit CM33 of the switch device SW32 is turned on, the switch unit CM34 of the switch device SW32 is turned off, and consequently the shift register signal SRO2 is transmitted to the second input end I8 of the shift register SR3 as the input signal SRI32.
The drawback of the conventional switch set 220 is that the control signals VBD and XBD have to respectively keep at the first predetermined voltage and the second predetermined voltage when the shift register circuit 200 is set to operate in the forward direction, and the control signals VBD and XBD have to respectively keep at the second predetermined voltage and the first predetermined voltage when the shift register circuit 200 is set to operate in the reverse direction. Due to the control signals VBD and XBD have to keep at a fixed predetermined voltage for long time, the fixed voltage will cause aging of the switch components, which in turn reduces the lifetime of the switch components, especially when the switch components are amorphous silicon (a-Si) thin film transistors (TFTs).